Commit c1f37710 authored by dauncey's avatar dauncey

Minor stuff

parent e81776e8
......@@ -6,6 +6,7 @@
#include <dlfcn.h>
#include <iostream>
#include <sstream>
#include <cassert>
......
......@@ -81,7 +81,7 @@ private:
int main(int argc, char* argv[]) {
bool var(true);
bool l25(false);
bool l25(true);
std::string fn("DumbTm");
if(var) fn+="Var";
......@@ -175,16 +175,43 @@ int main(int argc, char* argv[]) {
}
for(unsigned l(0);l<nL;l++) {
/*
l = total number of input links in each endcap
nInput = number of Stage 1 boards in each endcap
t = time multiplexing value
m = number of links from each Stage 1 FPGA to each Stage 2 FPGA
r = number of regions for each endcap
n1 = number of Stage 1 boards per region
nOverlap = number of links for duplication in each direction at boundary
(assuming a hard-coded number of 72 links here; CHECK)
Hence:
Number of Stage 1 boards = n1 x r
Number of Stage 2 boards = t x r
Limit on links out of Stage 1: m x t <= 72
Limit on links out of Stage 2: m x n1 <= 72
Each region has 2 x nOverlap duplicating links and so the number of
Stage 1 boards which each duplicate one link is 2nOverlap, and the number
which do no duplication is n1-2nOverlap. Hence number of links giving
actual region data = (n1 x m - 2nOverlap) and data volume over time
mplex period is = (n1 x m - 2nOverlap) x t.
*/
//for(unsigned l(0);l<nL;l++) {
for(unsigned l(0);l<=48;l+=48) {
//unsigned nLinks(l==0?3888:3500+100*l);
unsigned nLinks(3500+50*l);
unsigned nLinks(72*(24+l));
unsigned nInput((nLinks+71)/72);
std::cout << std::endl << "Number of input links/endcap = " << nLinks << std::endl;
std::cout << std::endl << "Number of input links/endcap = " << nLinks
<< ", number of Stage 1 boards = " << nInput << std::endl;
unsigned minCost(1000000);
unsigned minLatency(1000000);
for(unsigned t(1);t<=72;t++) {
for(unsigned t(6);t<=72;t+=6) { // Time mplex
std::cout << std::endl << "Links = " << nLinks << ", time mplex = " << t << std::endl;
if(l==0) {
std::ostringstream sLabel;
sLabel << std::setw(2) << std::setfill('0') << t;
......@@ -201,7 +228,7 @@ int main(int argc, char* argv[]) {
for(unsigned m(1);m<=72;m++) {
for(unsigned r(1);r<=72;r++) {
for(unsigned r(3);r<=6;r+=3) {
unsigned n1((nInput+r-1)/r);
System syst(nLinks,r,t,m);
......@@ -218,7 +245,7 @@ int main(int argc, char* argv[]) {
if(l25) ratio=((n1-2*nOverlap)*m*t+2*nOverlap*(m-1)*t)/(28.0*n1);
else ratio=((n1-2*nOverlap)*m*t+2*nOverlap*(m-1)*t)/(42.0*n1);
if(ratio>(var?1.4:1.1)) {
if(ratio>(var?1.4:1.1) || true) {
// Find latency, cost and overhead ratio
unsigned latency(t);
......@@ -235,10 +262,15 @@ int main(int argc, char* argv[]) {
<< cost << ", "
<< ratio << std::endl;
std::cout << "Number of Stage 1 boards with a duplication link = " << 2*nOverlap << std::endl;
std::cout << "Number of Stage 1 boards without a duplication link = " << n1-2*nOverlap;
hCvsKT[t-1]->Fill(2*nLinks,cost);
if(tmMinCost>=cost) {
std::cout << "New TM minimum cost" << std::endl;
std::cout << " New TM minimum cost";
tmMinCost=cost;
tmMinLatency=latency;
tmMinRegions=r;
......@@ -246,10 +278,12 @@ int main(int argc, char* argv[]) {
}
if(minCost>=cost) {
std::cout << "New minimum cost" << std::endl;
std::cout << " New minimum cost";
minCost=cost;
minLatency=latency;
}
std::cout << std::endl;
hCvsL[l]->Fill(latency,cost);
}
}
......
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